The capability to fabricate and interconnect large numbers of functional devices such as transistors, diodes, capacitors and resistors on a semiconductor substrate has lead to the availability of numerous diverse and often complicated integrated circuits. As the complexity of the circuits being fabricated increases, larger number of functional devices are being required on the substrate. Thus, the dimensions of the functional devices are being reduced, which makes the factors of interconnection of the devices and the planarization of the fabrication surfaces critical.
In the current technology, much of the interconnection of functional devices in an integrated circuit is done concurrently with their fabrication. In many cases, interconnection conductors may serve a dual role as a common node for two or more functional devices and as a convenient means for completing a complex maze of interconnections required for circuit functionality. For example, the diffusions necessary for the source and drain regions of transistors may be used as electrical conductors to interconnect nodes within a circuit. Similarly, the polysilicon lines commonly used to form gates for the same transistors may also provide suitable conductors for the creation of interconnections. Although convenient, these techniques have a significant drawback in that interconnection paths may infringe on silicon substrate area that is more suitably used for the creation of functional devices such as transistors and diodes. This problem is especially acute when large numbers of functional devices are required to form a desired circuit, and the available substrate area is at a premium.
Modern integrated circuit technology has advanced to the point where the dimensions of structures in the plane of the silicon are comparable to the thickness of the materials used in their fabrication. The topology thereby created introduces problems during subsequent stages of fabrication, such as contact formation and interconnection by metallization layers.
Field oxidation techniques used for providing isolation in polysilicon gate technology and the polysilicon gate itself, do not lend themselves to planar surfaces over which multiple layers of interconnection can be created. Specialized techniques have therefore been devised to form the required planarized surfaces. Planarization of the surfaces is an important factor which must be considered during the fabrication of circuits using a large number of very small functional devices.
The interconnection of device nodes in an integrated circuit is similar to the interconnection of nodes on a printed circuit board. In the printed circuit board technology, multiple layers of interconnect are obtained by keeping the surface of the board planar during fabrication. A major difference for similar multi-level interconnections in an integrated circuit technology is the presence of the transistor and diode nodes in the starting substrate. Fabrication of the transistors and diodes usually is more commonly dictated by the steps to create them without heavily weighing the subsequent need for planarity during the interconnection stage of integrated circuit fabrication.
Thus, a need has arisen for a means for the multiple layer interconnection of various isolated functional devices in an integrated circuit.